This invention relates generally to the field of integrated circuits. More specifically, the present invention relates to a system for designing physical layouts of integrated circuits.
When designing an integrated circuit, a designer will use various design tools to describe the elements and functions that will be incorporated into the device. For example, the designer may use a hardware description language such as VHDL. A hardware description language allows the designer to describe the functions that are to be performed, without necessarily specifying what elements to use to perform the function. Software tools are available to translate the hardware description language into a gate level design that specifies each element. Alternatively, the designer may enter the gate level design directly. For example, drawing tools are available for entering gate level designs. Such a design may be represented by a schematic that has symbols to identify each element in the design. In the schematic, every element that is intentionally in the design is represented by a symbol. Generation of the schematic may be accomplished manually or automatically.
In order to fabricate the integrated circuit, the schematic is translated into a physical layout. The physical layout is a description of how the design will be fabricated in the actual device. In other words, it is a physical representation of the elements in the schematic. Generating a physical layout is a time consuming process. Electronic design automation tools exist to generate a physical transistor layout with uniform gates. These types of gates are known as standard cells. However, in the case of non-standard cells, or custom cells, the layout engineer generates the physical transistor layout manually, for instance, by drawing it on a computer. For a typical integrated circuit, the time for generating a custom layout is measured in months.
The electronic design automation tools that are available to generate the physical layout from a schematic representation, typically divide the schematic design into sets of resources and nets. Each element and I/O port is defined as a resource and each connection between elements is defined as a net. For example, a transistor, a capacitor, I/O pad, or a resistor may be a resource and the connections between them may be nets.
The software places the resources among the standard cells in a layout and routes the nets between them. It will typically attempt to place the resources and nets such that a minimal area is consumed and the net lengths are minimized. Many different algorithms have been used to find the best placement and routing. However, as will be recognized, this is a well-known and difficult mathematics problem known as “The Traveling Salesman” problem. The solution to this problem is N-P complete. As such, an optimal solution is not possible in a reasonable amount of time when the number of resources and nets is high.
Because of their complexity, electronic design automation tools are typically very expensive and time consuming to run. The layouts they provide are generally of marginal efficiency. A human being can often place and route items much more efficiently. The results of these electronic design automation tools may need to be reworked manually to remove inefficiencies or for other reasons. Furthermore, these tools are especially not well-suited for designs that do not have many repeatable elements. Full-custom design is often in this category.
While there may be times that an electronic design automation tools of the type currently available today may be desirable, often their use is not desirable. Many improvements to accelerate the design process, improve the results, and give designers more control over the final layout are needed. In addition, for example, one area of concern in the integrated circuit industry is the design of test chips. A test chip is one that is typically used by integrated circuit manufacturer to determine the operating characteristics of certain devices, elements, or structures. Test chips may be used to test the fabrication processes and create models of the various elements used in the integrated circuits. These test chips generally have relatively few number of elements compared with a high number of input and output pads. Due to the nature of a test chip, it will generally have few repeating elements. In the specific example of test chips, the efficiency of the wiring and use of area in the layout is not as important as the speed with which the test chip can be created. In the past, it has sometimes taken months to produce such a test chip by hand.
Another example of when existing design tools may not be appropriate is when the circuit is small and density of design is not as important as the speed of completing the design. Often, only a small window of opportunity is given in the marketplace. It is more important to get a product out quickly, than to have a design that is designed in the smallest possible area. For such a situation, manual layout is not an good option because of time constraints, and autorouting software is not a good option because it adds a burdensome expense.
It is therefore desirable to have a new layout system for automatically generating a physical layout.